Hytec Electronics Ltd.

VMEBUS MADC 2508 Product Description The MADC 2508 is a dual height (6U) single width VME module which digitises 32 differential or 64 single–ended voltage signals with 16 bits resolution. Digitised values are stored in a 128K word memory. Scans of a programmed number of inputs are triggered either at programmed rates from 100kHz down to 10Hz, by hardware handshake or by soft trigger. The ADC has a good linearity and the ability to wait for amplifier settling times, according to programmed gain settings, before digitising commences. Features 32–channels true differential, 64–channels single-ended. Programmable 16 or 12 bits conversion resolution. Programmable trigger rate (100k, 20k, 5k, 1k, 200, 50, 10 scans per second) or external trigger. 128K x 16 buffer (4k/2k conversions per channel). Continuous or stop modes. Memory read/write random access. A 16/D16 configuration registers, A32/D16 memory, (Hytec protocol). Programmable gain, 1, 2, 4, 8, 16, 32 64 unipolar (positive or negative)/bipolar, filter and delay before conversion control on each channel. Maximum gain setting provides 160mV full–scale. Interrupt after preset number of conversions per channel. 2’s complement for bipolar operation (Sign extended for 12 bits).  Analogue signal connectors 37–way D types. Trigger connector 4 pin Lemo. Pipelined operation – mux settles on next input whilst conversion occurs. Front panel LEDs display status of trigger and VME access. Minimal links. Software control is maximised with all registers read/writeable. Test reference input facility – Reference Signals are routed to the amplifier in place of the multiplexer. Use of Address Modifiers AM29 - Access configuration registers. AM09 - Access conversion data memory if enabled. Memory The 128k x 16 bit SRAM is located in extended (a32) address space. The memory offset is set by the value stored in the memory offset configuration register bits 2–15.

The configuration registers occupy 64 bytes in the short address space above the base address which is determined by printed circuit

board address jumpers. These are mapped as follows:–

BA+3E Channel 32 Descriptor Channel 31 Descriptor Read/Write

BA+22 Channel 4 Descriptor     Channel 3 Descriptor Read/Write
BA+20 Channel 2 Descriptor     Channel 1 Descriptor Read/Write
BA+16 Trigger Rate                                                 Read/Write
BA+14 Number of Scans to Trigger                           Read/Write
BA+10 CA Pointer MS                                             Read/Write
BA+0E CA Pointer LS                                              Read/Write
BA+0A Channels per scan                                        Read/Write
BA+08 Memory attributes                                         Read
BA+06 Memory offset                                               Read/Write
BA+04 Control & status                                            Read/Write
BA+02 Device type                                                   Read
BA+00 Identifier/Vector                                             Read/Write

DB0     DB8     Gain 1
DB1     DB9     Gain 2
DB2     DB10    Gain 3
DB3     DB11    Filter Enable
DB4     DB12    Delay 1) 0=0
S 1=2
S
DB5     DB13    Delay 2) 2=4
S 3=8
S
DB6     DB14    Unipolar/Bipolar
DB7     DB15    +/–

Trigger Rate

D3–D0 A 4–bit code which defines the rate from 10Hz to 100kHz. Code 0 selects external/soft trigger. Code 15 disables trigger.

Number of Scans

DB15–DB0 A 16–bit value which sets the number of scans before interrupt.

Conversion Address

DB0 - DB3  Most significant bits of the Address.
DB0 - DB15 Least significant bit of the Conversion Address.

DB15–DB0 The least significant 16bits of the Block Transfer Address Pointer.

Vector

DB15–DB0 An 8 or 16–bit value determines the interrupt vector value.

DB7–DB0 Values of 1 to 64 determine the number of channels to be scanned.

DB15 and DB14 are asserted as a 1 to indicate RAM.`
DB13 is asserted as a 1 to indicate accessibility is both non–privileged and supervisory.
DB12 is asserted as 0 to indicate block transfer capability.
DB11 is asserted as a 1 to indicate non–protected mode.
DB10, DB9 are asserted as 0 and DB8 is asserted as a 1 to indicate 50–99ns speed.
DB7–0 are asserted as 1s.

DB15 to DB2 determine the memory offset mapped onto A31 to A18.
DB1 and DB0 are not used.

DB15 Scan done. Selected number of scans completed.
DB14 Reserved.
DB13 12 bit conversion data when set to 1. Default 16 bits.
DB12 Loop back to zero at end of scan.
DB11 Differential mode enable when set to 1.
DB10 Connect reference to the input when set to 1.
DB9 Soft trigger. Trigger preset number of scans.
DB8 ARM enables acquisition when set to 1.
DB7 Interrupt enable when 1.
DB6 Memory full. Interrupt if enabled.
DB5 Single scan. When set to 1 a single scan is enabled for each trigger.
DB4 )
DB3 ) Three bits set interrupt priority level.
DB2 )
DB1 Logic 1. The module does not drive Sysfail.
DB0 Writing a 1 resets the module. Reading a 1 means that acquisition is occurring.

DB11–DB0 define the device code = 2508.