What is the 2530?
This is a VME64 module which accepts up to eight voltage pulsed signals. It measures their peak heights and either counts the number of occurrences at certain peak heights for each input channel (histogram mode) or stores the conversions sequentially in its memory (list mode).

What are the pulses that it measures?
The input signals are ‘rounded top’ or Gaussian-shaped pulses. These are derived from radiation detectors such as scintillation (e.g. sodium iodide) or solid-state detectors (e.g. Ge-Li). They are in the form of charge pulses which are normally amplified and converted to voltages by front-end pre-amplifiers and amplifiers. The pulses are shaped to produce rise and fall times of different values. Shaping produces a well defined pulse which is relatively free from noise. Usually the rising edge is fast (50-200ns for solid-state and 200ns-1us for scintillation) with a slow falling edge which decays away exponentially and can be of the order of microseconds or tens of microseconds in the case of scintillation detectors.

How is the pulse measured?
When the input pulse starts to rise, at some point it exceeds a programmed voltage which determines the lower level discriminator setting. This is set to be above the noise threshold. When this voltage is exceeded the discriminator output opens a linear gate. This gates the pulse to a capacitor which charges up to the peak voltage. This stored voltage is compared with the input pulse and when it exceeds the amplitude of the input pulse, because the input tails away, the linear gate is closed and the peak voltage is held on the capacitor. The voltage stored on the capacitor is then buffered and switched to an ADC for conversion to a binary value.

Why is good integral and differential non-linearity important?
The measured voltage is proportional to the energy of the detected particle. The spectrum of energies present needs to be measured and it is important that there is a linear relationship between the different energies. This is defined by the integral linearity of the ADC.
The ADC converts the input voltages to 8K different values. The input voltage is a continuous variable and many voltages may have the same converted value. This range is termed a ‘bin’ and the width of the bin is determined by the differential non-linearity of the ADC. A pulse derived from a radiation detector will be subject to statistical variation and its value may be spread across several bins. Therefore, if a number of pulses derived from the same energy are converted and the conversions with the same values (i.e. falling within the same bin) are counted then the spectrum of the counts will be, ideally, Gaussian. If the bins vary greatly in width then the spectral shape will be distorted.

What is sliding-scale correction?
Most ADCs have a figure for differential non-linearity of 1/2LSB to 2LSBs. This represents a figure of 50-200%. In order to minimise the differential non-linearity a sliding-scale correction may be applied. This is done by adding a small varying waveform to the signal and then subtracting its digital value from the resultant conversion. Therefore the input voltage is varied across several bins so that with time the variation in bin width is averaged out. If the variation is 64 bins the differential non-linearity will be reduced from 50% to 50/64% or less than 1%. Other errors are involved – the DAC producing the varying summing voltage will also be non-linear. This may be reduced by increasing the resolution of the ADC and dividing down both the analogue output and the digital subtracted value. In practice 1-2% DNL is considered good.
Sliding scale over 64 bins = 6bits = 0- 0x3F of ADC
Volts/bit of ADC = 2.5/213 = 305.176uV
Thus 6bits = 0x3F x 305.176uV = 19.226mV

In the 8.191V range the shaker will move by 19.226mV x (8.191/2.5) = 62.992mV

The shaker injects a negative voltage as this allows a peak pulse at a max voltage of 8.191V to be digitised with out the shaker causing over ranging.
However if a peak pulse of less that approx 63mV then the shaker will take the voltage negative which will cause errors.

Why use a histogram mode?
When a radioisotope is detected it will produce pulses of different amplitudes depending on the escape energies of the detected particles. The isotope may be identified by a spectrum of energies and its mass can be calculated by the rate of emissions. Therefore it is necessary to count the pulses with similar amplitudes (related to energy) to form a spectrum of counts (frequency) vs bin number (energy). This provides an energy spectrum in which the radiation can be identified from the energy peaks and the activity by the integrated counts divided by the time to acquire them. This time must be the actual count time and should take into account the dead time of the ADC (live time = real time – dead time). Therefore, the time for which the ADC cannot accept a new pulse (dead time) must be indicated (Busy).
The individual gates associated with each input are used for coincidence gating. When the input pulse is in coincidence with its gate it is converted and the data recorded. If it is not in coincidence the pulse is rejected and a fast clear initiated to discharge the hold capacitor and reset the linear gate.

What is List mode?
List (or Gate) Mode uses the Master Gate input to initiate conversions. Any inputs that have a pulse present in coincidence with the gate are converted. The conversions are listed to memory with formatting words to provide header, number of channels converted, conversion value and channel number, end-of-block and event count. Each gate pulse is counted in order to provide the event count.

Product Description

The Hytec ADC2530 is a VME module that provides 8 channels of peak-sensing voltage digitisation with the following characteristics:-

• 8 pulse inputs
• Single sampling ADC and 8-input multiplexer
• 13 bits resolution (8000 channels)
• Sliding-scale correction of differential non-linearity
• +/-2% differential non-linearity
• +/- 0.025% linear non-linearity
• 0V - 8.191V input range (positive or negative-going, jumper selectable)
• 1k / 50R input impedance jumper selectable
• On-board dual-port SRAM
• Code format straight binary
• List or histogram modes
• Event counter for list mode
• Self-triggering or Gated modes
• 3us conversion and readout time per input
• Front panel Gate, Fast clear, Data ready, Busy NIM/ECL signals
• Two DAC settings for common Lower Level and Upper Level discrimination.
• Front panel Lemo 00 co-axial connectors
• Front panel LED status indication

Power Requirements

+5V @ 300mA
+12V @ 200mA (quiescent)
-12V @ 200mA (quiescent)
1.2 Operating Temperature Range
0 to +45 deg Celsius ambient.
1.3 Mechanical
6U single width VME module with access to P1 and P2 connectors.
1.4 Front Panel Indicators
'VME' LED (green) illuminates for a minimum of 100msecs whenever the module is accessed via the VME bus.
'ARM' LED (red) indicates that the module is Armed and is acquiring data.
'BUSY' LED (red) indicates that an input pulse has been accepted and is being converted.
'GATE' LED (red) illuminated when the module is in Gate mode.
‘INTR’ LED (red) indicates that an interrupt is pending.
‘CONFIG’ LED (blue) indicates that the module is powered and configured.

Signal Specifications

Pulse Inputs 1-8
Connector type: Lemo 00 socket isolated from panel. Centre pin-Signal, Outer-AGND.
Signal: Pulse with rounded top
Span: 0 to 8.191V (1mV per channel). Polarity jumper selectable
Rise time: 100ns – 20us for accurate peak detection.
Input impedance 1K/50R jumper selectable.
ADC resolution: 13 bits (8000 channels with sliding-scale correction).
Diff. non-linearity: +/-2% (over 99% of range).
Int. non-linearity: +/-0.025% (over 99% of range).
Offset error: +/-1LSB.
Gain Error: +/-1LSB
Gain Drift: +/-20ppm per deg C
Offset Drift: +/-2ppm per deg C
ADC conversion : 3uS per input.
Dead time: 1us-20us depending on mode and input usage
Gate period: 20ns-20us

Gate Input (Gates 1-8 and Master Gate)
Connector type: Lemo 00 socket
Signal: NIM/ECL
Causes conversion of input pulses coincident with Gate pulse in Gate mode
Master Gate applies to all inputs. Individual gates allow conversions on coincident channels in Histogram mode.
Fast Clear Input
Connector type: Lemo 00 socket
Signal: NIM/ECL
Clears all peak detectors to zero within 50ns
Busy Output
Connector type: Lemo 00 socket
Signal: NIM/ECL
Output signal generated when a pulse is accepted and remains true until all circuits are free to accept a new input
Data Ready Output
Connector type: Lemo 00 socket
Signal: NIM/ECL
Asserted when any Half-full or Full flag is set and can be cleared by writing to Full or Half-Full flags in Fullness register.

Operating Modes
Self Triggering
A pulse received on any input if it is within the lower and upper level discriminator settings will cause the peak value detected to be digitised.
List Zero Enable
A pulse received on any input if it is within the LLD and ULD settings and coincident with the Gate pulse will cause the peak value detected to be digitised. If the Zero Enable bit is set in the CSR, those channels which do not convert will record a zero conversion.
Histogram Memory
Eight memory banks accumulate a spectrum of sample frequency vs channel number (conversion value) for each input. The spectra are each 8Kx32 bits. When any channel overflows acquisition on that input is halted until the Full flag is cleared.
List Memory
Conversions are listed into memory which acts as a FIFO. Each of the eight FIFOs has a Half Full and a Full flag. In LIST Mode, the memory is one contiguous FIFO with a Half Full and a Full flag.
 

Ordering Information
Cat No:2530  Name: NADC2530  Description: 8-channel 13-bit ADC with 8K Memory per channel for Listing/Histogram