Hytec Electronics Ltd |
512K Sample Octal or 1M Sample Quad 14bit 10MHZ Transient Recorder Product Description The VTR 2536T-4M Transient Recorder is a dual height single width VME module which simultaneously samples and digitises the voltage signals present on either eight or four inputs (jumper selectable) with a resolution of 14 bits and records the data sequentially in its on-board SRAM giving 512K or 1M samples per channel respectively. The SRAM is accessible from the VME bus when the module is not acquiring data. An interlock between its Busy and Memory Access control bits ensure that there is no conflict of access. An interrupt is generated whenever the acquisition is stopped and interrupts enabled. Acquisition can be halted either by a software Stop command, a Triggered Stop or when the memory is full. The sample clock may be internally generated at programmed rates of 1, 2, 5 or 10 MHz. The module can also accept an external clock via a front panel two-pin connector. The module accepts an External Trigger via a front panel connector. The trigger input signal can be programmed to act as a simple trigger (pulse input) or as a triggered Start and Stop signal (using signal levels). Front panel LEDs indicate the status of Start, Stop, VME access and External Clock Enable conditions. The module can be operated in a number of different modes by writing to on-board control registers. The basic modes of operation are:-
Address Modifiers
Power Requirements +5V @ 600mA, +12V @ 250mA, -12V @ 350mA Operating Temperature Range 0 to +45 deg Celsius ambient. Mechanical 6U single width VME module with access to P1 and P2 connectors. |
Front Panel Indicators
'VME' | LED (green) illuminates for a minimum of 100msecs whenever the module is accessed via the VME bus. |
'Start' | LED (green) indicates that Start is set either by software command or by front panel trigger. |
'Stop' | LED (red) indicates that acquisition has been stopped either by software command or when the memory is full or by front panel trigger. |
'External' | LED (yellow) illuminated when the external clock is enabled. |
Signal Specifications
External Clock
Connector type: | 0302 |
Signal: | Differential ECL or single TTL. |
Connector type: | 00250 |
Signal: | Single TTL or ECL. Rise time < 20nS |
Connector type: | 0302 Pin 1+, Pin 2-, Screen common. |
Signal: | Differential +/- with screen (capasititivly AC coupled to chassis ground) |
Span: | 0 to 2V unipolar +/-2V, bipolar as determined by PCB jumpers. |
CMRR: | 70dB |
CMV: | +/-5V |
Input impedance: | 1K/100R jumper selectable. |
ADC resolution: | 14 bits. |
Diff. non-linearity: | +/-1 LSB. |
Int. non-linearity: | +/-2.5 LSB. |
Offset error: | +/-1 LSB. |
Zero drift: | 5ppm per deg C |
Gain drift: | 7ppm per deg C |
Bandwidth (ADC): | 50MHz |
Transient response: | 50nS typical for 2V step(1LSB) |
SNR: | 78dB at 5MHz typical. |
SINAD: | 77dB at 5MHz typical. |
ADC aperture delay: | 1nS typical (system delay 2.2ns typical). |
ADC aperture jitter: | 4pS typical (system jitter 8ps typical). |
Use of the VME Data-Bus and Memory Access
Base AddressThe module uses A16/D16/D8 (EO) (Even and Odd byte) for accesses to the configuration registers. The base address of the configuration registers is determined by PCB jumper settings (J33=A6 to J26=A12).
A15 |
A14 |
A13 |
A12 |
A11 |
A10 |
A09 |
A08 |
A07 |
A06 |
A05 |
A04 |
A03 |
A02 |
A01 |
A00 |
1 |
1 |
J26 |
J27 |
J28 |
J29 |
J30 |
J31 |
J32 |
J33 |
X |
X |
CA |
CA |
CA |
0 |
Addresses are in the range C000 - FFFE
A06 - A13 is the module address determined by the setting of the relevant PCB
jumpers (J33=A6 to J26=A12).
A00 - A03 is the particular configuration register address (e.g. C000 is ID).
The unit has 4Meg of on board SRAM and uses
address lines A23 to A31. The units base address is stored
as an offset in the Memory Offset register.
A jumper(J25 see appendix A) is used to select between 4 channels giving 1Meg of
samples per channel and 8 channels giving
512k samples per channel. The setting of the jumper can be ascertained by read
the Device Type register at base +2.
The unit also supports 32 bit VME block transfer mode BLT for memory access.
Memory data may be accessed as bytes, words or longwords using A32/D32/D16/D8 (EO).
Words and bytes are accessed via D15-D00. A1 addresses the low order word of a
longword, A0 thehigh order word (big endian), thus A0 accesses the first
conversion, A1 the second, and so on.
Conversions for each ADC are word ordered from 0 to 512K as shown: -
Memory top = Base + 4M words
D31 |
D16 |
D15 |
D00 |
ADC8 1st to (512K-1)th conversions 256Kx16 |
ADC8 2nd to 1Mth conversions 256Kx16 |
ADC7 1st to (512K-1)th conversions 256Kx16 |
ADC7 2nd to 1Mth conversions 256Kx16 |
ADC6 1st to (512K-1)th conversions 256Kx16 |
ADC6 2nd to 1Mth conversions 256Kx16 |
ADC5 1st to (512K-1)th conversions 256Kx16 |
ADC5 2nd to 1Mth conversions 256Kx16 |
ADC4 1st to (512K-1)th conversions 256Kx16 |
ADC4 2nd to 1Mth conversions 256Kx16 |
ADC3 1st to (512K-1)th conversions 256Kx16 |
ADC3 2nd to 1Mth conversions 256Kx16 |
ADC2 1st to (512K-1)th conversions 256Kx16 |
ADC2 2nd to 1Mth conversions 256Kx16 |
ADC1 1st to (512K-1)th conversions 256Kx16 |
ADC1 2nd to 1Mth conversions 256Kx16 |
Memory base = Value in Memory Offset Register.
Conversions for each ADC are word ordered from 0 to 1Meg as shown:
Memory top = Base + 4M words
D31 |
D16 |
D15 |
D00 |
ADC8 1st to (1M-1)th conversions 512Kx16 |
ADC8 2nd to 1Mth conversions 512Kx16 |
ADC6 1st to (1M-1)th conversions 512Kx16 |
ADC6 2nd to 1Mth conversions 512Kx16 |
ADC4 1st to (1M-1)th conversions 512Kx16 |
ADC4 2nd to 1Mth conversions 512Kx16 |
ADC2 1st to (1M-1)th conversions 512Kx16 |
ADC2 2nd to 1Mth conversions 512Kx16 |
Memory base = Value in Memory Offset Register.
Memory Data
D31 |
D30 |
D29 |
D28 |
D27 |
D26 |
D25 |
D24 |
D23 |
D22 |
D21 |
D20 |
D19 |
D18 |
D17 |
D16 |
0 |
O/R |
AD 13 |
AD 12 |
AD 11 |
AD 10 |
AD 09 |
AD 08 |
AD 07 |
AD 06 |
AD 05 |
AD 04 |
AD 03 |
AD 02 |
AD 01 |
AD 00 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D09 |
D08 |
D07 |
D06 |
D05 |
D04 |
D03 |
D02 |
D01 |
D00 |
0 |
O/R |
AD 13 |
AD 12 |
AD 11 |
AD 10 |
AD 09 |
AD 08 |
AD 07 |
AD 06 |
AD 05 |
AD 04 |
AD 03 |
AD 02 |
AD 01 |
AD 00 |
ADxx denotes ADC conversion data bit
O/R denotes out of range bit
Address Modifiers
Configuration Registers:AM29 or 2D (short
non-privileged or supervisory)
Memory: AM09 or 0D (extended non-priv. or supervisory)
BTL: AM0B or 0F (extended non-priv. or supervisory
Firmware Registers
Address: Base + 00
Manufacture ID 8063
ID | (Read) |
Address: | Base + 00 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D09 |
D08 |
D07 |
D06 |
D05 |
D04 |
D03 |
D02 |
D01 |
D00 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
Device Type | (Read) |
Address: | Base + 02 |
1Meg = 12536
D15 | D14 | D13 | D12 | D11 | D10 | D09 | D08 | D07 | D06 | D05 | D04 | D03 | D02 | D01 | D00 |
0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
512K = 22536
D15 | D14 | D13 | D12 | D11 | D10 | D09 | D08 | D07 | D06 | D05 | D04 | D03 | D02 | D01 | D00 |
0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
Control and Status Register (CSR)
Control | (Write) |
Address: | Base + 04 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D09 |
D08 |
D07 |
D06 |
D05 |
D04 |
D03 |
D02 |
D01 |
D00 |
A32 |
T2 |
T1 |
T0 |
ARM |
RP10 |
RP9 |
RP8 |
I.E. |
F |
RB |
C |
SP |
ST |
PT |
Rst |
Status | (Read) |
Address: | Base + 04 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D09 |
D08 |
D07 |
D06 |
D05 |
D04 |
D03 |
D02 |
D01 |
D00 |
A32 |
T2 |
T1 |
T0 |
ARM |
RP10 |
RP9 |
RP8 |
I.E. |
F |
RB |
C |
SP |
ST |
PT |
Bsy |
A32 | Enables memory access from VME when set to a 1. |
Disables ADC data acquisition. | |
T2 | Set sample clock bit 2 ( 000 - external; 001 - 1 MHz, 010 - 2MHz ) |
T1 | Set sample clock bit 1 ( 011 - 5MHz; 100 - 10MHz ) |
T0 | Set sample clock bit 0 |
ARM | Enable hardware triggered START and STOP and clears the conversion address to zero. |
RP10 - RP8 | Select/set reset interval for ADC latency compensation |
RP10 |
RP9 |
RP8 |
Reset interval latency compensation |
0 |
0 |
0 |
Disable ADC latency compensation |
0 |
0 |
1 |
800ns ® 850ns |
0 |
1 |
0 |
1.60m s ® 1.65m s |
0 |
1 |
1 |
3.2m s ® 3.25m s |
1 |
0 |
0 |
12.8m s ® 12.85(s |
1 |
0 |
1 |
51.2m s m 51.25® s |
1 |
1 |
0 |
409.6m s m 409.65® s |
1 |
1 |
1 |
1.23ms m 1.23005ms |
External clock low periods to reset latency compensation.
IE | Interrupt Enable - An IRQ is generated if Stop is set. |
The IRQ number is determined by PCB jumper settings. | |
F | Full flag - Set when the memory has been completely filled. |
RB | Ring Buffer Mode - Stop is not set when Full is set when RB=1 |
Acquisition continues with the conversion address wrapping around. | |
C | Continue acquisition from the point where it was last stopped. |
SP | Stops acquisition (drives front panel STOP led). |
SP is set by: memory full (RB is not set), triggered stop, or pre-set count Stop. | |
ST | Starts acquisition (drives front panel START led) and clears the conversion address to |
zero. If PT is set acquisition is confined to the lower 64K of memory until Trigger if PT | |
is not set ST may be set by command or by Trigger whereupon conversions will fill the memory. | |
PT | Enables Pre-trigger acquisition. |
Busy | Set when acquisition is started or continued. |
Inhibits A32 from being set (i.e. disables VME memory accesses). | |
Rst | Clears status register to zero. |
Memory Offset (Read/Write)
Address: | Base + 06 |
VTR 2536-4M |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D09 |
D08 |
D07 |
D06 |
D05 |
D04 |
D03 |
D02 |
D01 |
D00 |
A31 |
A30 |
A29 |
A28 |
A27 |
A26 |
A25 |
A24 |
A23 |
x |
x |
x |
x |
x |
x |
x |
Conversion Address or Sample Counter (LS) (Read)
Address: | Base + 08 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D09 |
D08 |
D07 |
D06 |
D05 |
D04 |
D03 |
D02 |
D01 |
D00 |
M15 |
M14 |
M13 |
M12 |
M11 |
M10 |
M09 |
M08 |
M07 |
M06 |
M05 |
M04 |
M03 |
M02 |
M01 |
M00 |
Conversion Address or Sample Counter (MS) (Read)
Address: | Base + 0A |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D09 |
D08 |
D07 |
D06 |
D05 |
D04 |
D03 |
D02 |
D01 |
D00 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
M19 |
M18 |
M17 |
M16 |
The conversion address registers gives the acquisition address in a 16bit format, which is also the number of logged samples.
Address: | Read = Base + 0C |
Write = Base + 00 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D09 |
D08 |
D07 |
D06 |
D05 |
D04 |
D03 |
D02 |
D01 |
D00 |
V15 |
V14 |
V13 |
V12 |
V11 |
V10 |
V09 |
V08 |
V07 |
V06 |
V05 |
V04 |
V03 |
V02 |
V01 |
V00 |
Trigger Address / Triggered STOP Address (LS) (Read/Write)
Address: | Base + 0E |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D09 |
D08 |
D07 |
D06 |
D05 |
D04 |
D03 |
D02 |
D01 |
D00 |
T15 |
T14 |
T13 |
T12 |
T11 |
T10 |
T09 |
T08 |
T07 |
T06 |
T05 |
T04 |
T03 |
T02 |
T01 |
T00 |
Trigger Address / Triggered STOP Address (MS) (Read/Write)
Address: | Base + 10 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D09 |
D08 |
D07 |
D06 |
D05 |
D04 |
D03 |
D02 |
D01 |
D00 |
T31 |
T30 |
T29 |
T28 |
T27 |
T26 |
T25 |
T24 |
T23 |
T22 |
T21 |
T20 |
T19 |
T18 |
T17 |
T16 |
The data held in these registers is the triggered address or the triggered stop address in a 32 bit format.
Pre-set Count Register (LS) (Read/Write)
Address: | Base + 12 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D09 |
D08 |
D07 |
D06 |
D05 |
D04 |
D03 |
D02 |
D01 |
D00 |
P15 |
P14 |
P13 |
P12 |
P11 |
P10 |
P09 |
P08 |
P07 |
P06 |
P05 |
P04 |
P03 |
P02 |
P01 |
P00 |
Pre-set Count Register (MS) (Read/Write)
Address: | Base + 14 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D09 |
D08 |
D07 |
D06 |
D05 |
D04 |
D03 |
D02 |
D01 |
D00 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
P19 |
P18 |
P17 |
P16 |
The value written to this register will give the number of samples that will be taken before the Stop bit of the CSR is set to one.
Triggered Start Address (LS) (Read/Write)
Address: | Base + 16 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D09 |
D08 |
D07 |
D06 |
D05 |
D04 |
D03 |
D02 |
D01 |
D00 |
TS15 |
TS14 |
TS13 |
TS12 |
TS11 |
TS10 |
TS09 |
TS08 |
TS07 |
TS06 |
TS05 |
TS04 |
TS03 |
TS02 |
TS01 |
TS00 |
Triggered Start Address (MS) (Read/Write)
Address: | Base + 18 |
D15 |
D14 |
D13 |
D12 |
D11 |
D10 |
D09 |
D08 |
D07 |
D06 |
D05 |
D04 |
D03 |
D02 |
D01 |
D00 |
TS15 |
TS14 |
TS13 |
TS12 |
TS11 |
TS10 |
TS09 |
TS08 |
TS07 |
TS06 |
TS05 |
TS04 |
TS03 |
TS02 |
TS01 |
TS00 |
A VME system reset will clear the following registers:
· Control Register
· Status Register
· Memory Offset Register
· Vector Register
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