Hytec Electronics Ltd

Data Acquisition and Control

Octal 12bit 60MHz Transient Recorder

VTR 2537

Product Description

The VTR 2537 Transient Recorder is a dual height single width VME module which digitises the voltage signals present on eight inputs with a resolution of 12 bits and records the data sequentially in its on-board SRAM which accepts up to 1M samples per channel.

The memory is accessible from the VME bus when the module is not acquiring data. An interlock between its Busy and Memory Access control bits ensure that there is no conflict of access.

An interrupt is generated whenever the acquisition is stopped and interrupts enabled. Acquisition can be halted either by a Software Stop command, a Triggered Stop, after a pre-set number of samples have been stored or when the memory is full.

The sample clock may be internally generated at programmed rates of 1, 10, 20 or 50 MHz. The module can also accept an external clock (60MHz max) via a front panel two-pin connector. Different clock rates may be selected for pre or post-trigger.

The Transient Recorder module accepts an External Trigger via a front panel connector. The trigger input signal can be programmed to act as a simple trigger (pulse input) or as a triggered Start and Stop signal (using signal levels).

Front panel LEDs indicate the status of Arm, Busy (Triggered), VME access and External Clock Enable conditions.

The Transient Recorder module can be operated in a number of different modes by writing to on-board control registers. The basic modes of operation are:-

· Software driven acquisition where acquisition is started and stopped by writing to a Control register on the unit.
· Pre-triggered sampling where the memory is divided into two areas, the first is allocated to pre-trigger samples and the other to post-trigger samples. When the Pre-trigger mode is enabled, data is acquired into the pre-trigger circulating buffer. A change in state at the Trigger input causes the current conversion address of the pre-trigger buffer to be latched in the Trigger Address register so that data can be re-constructed up to the point of trigger. Conversions are then stored in the upper half of the memory until it is full or for a preset number of samples.
· Multi-segment mode in which the memory may be sub-divided into many circulating pre-trigger and post-trigger buffer pairs. The segments are then stepped through on each trigger with the trigger addresses stored in memory.
· A hardware Gate mode. Here the trigger input enables the acquisitions when true, and stops the unit acquiring when logic 0.
· The module can also be set to log a pre-set number of samples, and Stop. This can be started by software or hardware triggering.
· Ring Buffer mode. This is where acquisition cycles round the memory until a stop command is issued either by software or by hardware. The ring buffer mode can be set in any of the above modes apart from the pre-trigger sampling mode.

Full specification of VTR 2537 in Adobe .pdf format.

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Last modified: October 29, 2008