Hytec Electronics Ltd.

VME Serial Highway Driver Type VSD2992

Driver available from the EPICS community


Features

  • Operates as a VME Slave module A16/D16 D08(E0).
  • Operates as a VME ROAK D08 Interrupter.
  • Overall Interrupt Enable Bit.
  • Interrupt Selectable 1–7 by Jumper.
  • Vector Writable and Readable.
  • Complies with CAMAC specification EUR6100E and I.E.E.E. 595.
  • Bit Serial and Byte Serial Modes at up to 5MHz.
  • Internal Crystal Controlled or Variable Clock source, or external clock input with comprehensive dividing network on selected source.
  • Separate Reply Buffer.
  • 64 Word FIFO Demand Buffer.
  • Lost Sync Indicator.
  • 12 Bit Maskable LAM Register with front panel display.
  • Repeat Read Mode.
  • Q–Scan Mode.
  • Reply Timeout.
  • Echo Mode.
  • Readout of transmitted message.
  • 64 ’Byte’ Test Message Generator with facilities for forcing errors.
  • Module Booking mechanism for multi–master working.
  • Dump Store for message analysis.
  • Drive for Hytec U–Port Adaptor.
  • Readout of U–Port Setting & Main/Backup Loop States.

Software Drivers are available including Driver available from the EPICS community.

Product Description

The Hytec VSD2992 is a single width 6U VME Module which transmits and receives signals on the CAMAC serial highway whilst being controlled via the VME BUS. Bit serial and Byte serial ports for data and clock are provided for the transmission of command and the acceptance of reply and demand messages. Serial messages are initiated by loading command and data registers via the VME bus using either D16 or DØ8(E0) mode. Incoming messages are checked for transverse and longitudinal parity. The serial clock can be controlled by a crystal source, variable frequency oscillator or an external source. The internal oscillators may be divided down from the sources to give approximately 1kHz to 5MHz. The external source may range from slow frequencies to a maximum of 5MHz.

A twelve–bit ”Lam” Status and ”Lam” mask register–set provide a comprehensive interrupt system which has an overall allow interrupt bit. The Lam status register may be cleared or selectively cleared and the Lam mask register can be written, cleared, selectively set and selectively cleared. The mask and all control registers are cleared at power up or by a bus reset.

Operational Features

Six registers provide communications between the VME BUS and the Serial Highway. Message transmission is initiated by:
  • Writing the command register with a serial Read or Command function or
  • Writing the Write Data register whilst the Command register contains a serial Write function.
Loading the Command register with a serial Write Command does not initiate transmission. The 24 Bit Serial Read Data may be read via the VME bus as two 16 Bit words after the reply message has been received.

Receipt of a reply or otherwise together with the state of the serial SX and SQ may be determined by reading the unit status register (offset – Ø4). The full status is obtained by reading offset 16. A new transfer should not be set–up until a reply has been received for the previous transmission.

Two bits are provided in the command register so that a Q–scan mode may be utilised if the basic parameters, function, crate are the same. The two bits are MQ and MR.

If MR is set, then a ’Read” to the module initiates a repeat message. The serial Command sent, is identical if MQ=0, but is varied if MQ=1 depending on the state of the serial Q(SQ).

If SQ=1 then the serial address (SA) is incremented, whereas if SQ=0, SA is reset and the Serial station number (SN) incremented.

If SN increments beyond 24, then the crate address is cleared and the new transmission made with crate = 0. This gives address not recognised on receipt back at the SHD 2992 which interrupts terminating the transfer.

Timeout

If 350mS elapses from the start of a message transmission and there has been no reply or unrecognised command message, the TIMEOUT signal is asserted which sets TMO LAM source. SHR also becomes true (SHR = RPL or TIMEOUT) and the RDY LAM source is set if/when CMD is true. Reply messages received after TIMEOUT is asserted are ignored.

Addressing the Module

The module has its addressing structure similar to the VXI system and as such is an A16/D16/D08(E0) device. The unit status register (Ø4) contains a booking bit, which is automatically set following a read, if previously unset.

D08 (E0) may only be used if the order of Byte transmission can be controlled, otherwise incomplete messages may be propagated as the message is started when the unit detects the least significant data has been loaded. The following tables gives the provisional register allocation:


Our policy is one of continuous product development and the right is reserved to supply equipment which may vary slightly from that described.



Hytec Electronics Ltd
Post : 5 Cradock Road, Reading, Berkshire, RG2 0JT, England.
Phone : +44 (0)118 9757770
Fax : +44 (0)118 9757566

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Last modified: September 24, 2008